winjer
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AMD Ryzen 9 9950X3D and 9900X3D to Feature 3D V-cache on Both CCD Chiplets
Earlier this week, we got rumors that AMD is rushing in the Ryzen 7 9800X3D 8-core/16-thread "Zen 5" processor with 3D V-cache for a late-October debut. The 9800X3D succeeds the popular 7800X3D, and AMD probably hopes it will have a competitive gaming processor in time for Intel's Core Ultra...
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Earlier this week, we got rumors that AMD is rushing in the Ryzen 7 9800X3D 8-core/16-thread "Zen 5" processor with 3D V-cache for a late-October debut. The 9800X3D succeeds the popular 7800X3D, and AMD probably hopes it will have a competitive gaming processor in time for Intel's Core Ultra 2-series "Arrow Lake-S" launch. In the previous article, it was reported that the higher core-count 9000X3D series processor models, the Ryzen 9 9950X3D and Ryzen 9 9900X3D, would arrive some time in Q1 2025, because it was reported that the chips have certain "new features" compared to their predecessors, the 7950X3D and 7900X3D. At the time, we even explored the possibility of AMD giving both 8-core CCDs on the processor 3D V-cache. Turns out, this is where things are headed.
A new report by Benchlife.info claims that the higher core-count 9950X3D and 9900X3D will implement 3D V-cache on both CCD chiplets, giving these processors an impressive 192 MB of L3 cache (96 MB per CCD), and 208 MB or 204 MB of "total cache" (L2+L3). The report also says that AMD is planning a Ryzen 5 9600X3D chip, its second attempt at taking on Intel's Core i5 lineup, following its very recent release of the Ryzen 5 7600X3D, which ended up 1-3% short of the Core i5-14600K in gaming workloads. There's no word on whether the 9600X3D will launch in October alongside the 9800X3D, or in Q1-2025 with the Ryzen 9 9000X3D series.
The introduction of 3D V-cache on both CCDs of the 9950X3D and 9900X3D could be interesting, as both chiplets will be capable of gaming workloads at a uniform performance level. On the 7950X3D and 7900X3D, OS scheduler-level QoS logic ensure gaming workloads are scheduled to the CCD with the 3D V-cache, while multithreaded productivity workloads are allowed to spread across both CCDs.
That is a lot of cache. But how much cash will this cost?